Field of the Invention
The invention is related to a digital signal processor, which can interpret the receptive digital signals into the perceptive output digital signals. In particular, the processor parallel processes digital information according to its pre-configured digital content and perceptive non-volatile memories without executing any sequential Boolean logic operations. That is, instead of executing the combinational logic computations given by the programmed instructions in the conventional digital processors, the invented digital signal processor intelligently processes digital information fully based on their configured content and perceptive non-volatile memory hardware.
Description of the Related Art
In the modern Von Neumann computing architecture as shown in FIG. 1, the Central Process Unit (CPU) executes logic operations according to the instructions and data from the main memory 11. The CPU 10 includes a main memory 11, an arithmetic and logic unit 12, an input/output equipment 13 and a program control unit 14. Prior to the computation process, CPU 10 is set by the program control unit 14 to point to the initial address code for the initial instruction in the main memory 11. The digital data are then processed with the arithmetic and logic unit 12 according to the sequential instructions in the main memory 11 accessed by the clock-synchronized address pointer in the program control unit 14. In general, the digital logic computation process for CPU 10 is synchronously executed and driven by a set of pre-written sequential instructions stored in the memory.
The power consumption for digital computations is given by P˜f×C×VDD2, where f is the clock frequency, C is the total active circuit capacitance and VDD is the positive voltage supply for digital circuitries. Accordingly, the energy requirement for running a computation sequence is proportional to the numbers of clock steps to complete the set of instructions. Each instruction step includes fetching the instruction and data from the main memory 11, executing the micro-operations in the arithmetic and logic unit 12, and storing the resultant data back to the main memory 11 or outputting to the I/O (Input/Output) equipment 13. The total computation energy for completing a set of instructions is proportional to the frequency of memory accessing and the charging/discharging the total capacitances of the bus-lines and the active digital circuitries (registers, logic gates, and multiplexers). The more frequent memory accessing to complete the computation processing steps, the more energy and processing time are consumed for the digital processors.
While for a biologic nerve system the external stimuli such as lights, sounds, touches, tastes, and smells, are received by the fields of sensory organs connected to the nerve system. The neural signals in the forms of electrical pulses and neural transmitters (molecules) generated in the receptor fields are propagated to trigger the activation of next connecting layer of the neural network in the nerve system. The field of neural signals generated from the connecting layer continues to process forward throughout the multiple layers of the neural network hardware in the nerve system. Each neural network layer is parallel processing and extracting the information according to its neuromorphic structures and the receptive fields of neural signals from the previous layers. Unlike the present Von Neumann computing system iterating multiple logic computations for digital data by the pre-written instructions, the neural signals for information processing are propagated layer-to-layer in one-step feed-forward fashion by their neuromorphic structures. Therefore, in terms of information processing efficiencies and energy consumptions, the parallel processing and extracting information for layers of neural network in biologic nerve systems are superior to the processing and extracting information by multiple sequential logic computations in the present computing systems.
Inspired by the neural network information parallel processing, we are motivated to invent a digital signal processor analogous to the information processing in neural network systems directly by the processor's memory hardware for parallel processing digital signals within one feed-forward step. A digital symbol for digital information processing is generally represented by a string of bits (binary digits) in the combination of “0s” and “1s”, where the signals of “1” and “0” are provided by the applying positive voltage VDD and the ground voltage VSS in digital circuitries respectively. An input digital symbol with multiple bits representing specific input content information can be intelligently processed to output another digital symbol representing the perceived information by the processor. The processor is given by the name of “Digital Perceptron”. The meaning of “intelligently processed” is that the perceptive information is autonomously processed with the input digital “content” according to a pool of known knowledge of digital “contents”. In contrast to the “content” processing, CPU processes information with logic operations and memory by pointing to the “address” locations and the logic contents of look-up-tables in FPGA (Field Programmable Gate Array) are extracted for digital processing by configuring their “address” multiplexers as well.
The digital perceptron can be configured to store a group of digital symbols and the correspondent output digital symbols in the non-volatile memory units similar to the built-in neural network hardware. The group of digital symbols can represent various scenarios in real world as the digital contents. The correspondent output digital symbols could be digital commands to drive an analog device or the input digital symbols for other digital perceptrons. For instance, a group of digital symbols could represent the digital IDs for a group of people and the correspondent output digital symbols are the two digital commands for “grant” or “deny” the access to a facility. When a person tries to access the facility, the signals of the digital symbol representing the person's digital ID are read and broadcasted into the non-volatile memory database configured with the digital symbols representing the digital IDs for the entire group of people. When the input digital symbol signals are matched with one of the configured digital symbols, the correspondent pre-configured digital command signals are immediately sent out to grant or to deny the person to access the facility. That is, the digital perceptron recognizes the person immediately by his/her digital ID and decides to let him/her access the facility or the opposite.
Upon applying the same scenario with the present computing architecture, the input digital symbol for the person's ID is fed to perform a binary search in the non-volatile memory database storage, where the group's digital symbols and their correspondent digital commands are stored and can be accessed only by the clock-driven memory addresses. The binary search operation for CPU then applies the bit comparison with the logic gate XOR, where the two input bits with “equal logic value” and “non-equal logic values” yield logic “0” and “1” respectively. Therefore, to perform the binary search for a digital symbol with plural bits requires multiple times of bit-data transmissions and comparisons between the “XOR” logic gate units and the memory in CPU, and data transmissions between CPU I/O equipment and non-volatile memory database storage. The energy and time consumed for searching a digital symbol by addresses in a large memory database storage become very inefficient as the general practice of running programmed software algorithm with many times of memory accessing between CPU and non-volatile memory database storage, and the data comparisons in the present computing system.
In another aspect of this invention, the multiple-time configurability of non-volatile memories in the digital perceptrons provides the capability of real-time updating the digital content and output symbols. The digital content and output symbols can be renewed anytime according to the coding efficiency and the learning algorithms for the real world scenarios. From the perspective, the digital perceptron can evolve into a processor for better processing efficiency and more desirable functions set by the learning algorithm as the training for the processor.